\doxysection{TPI\+\_\+\+Type Struct Reference}
\hypertarget{struct_t_p_i___type}{}\label{struct_t_p_i___type}\index{TPI\_Type@{TPI\_Type}}


Structure type to access the Trace Port Interface Register (TPI).  




{\ttfamily \#include $<$core\+\_\+armv81mml.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\+\_\+\+\_\+\+IM uint32\+\_\+t \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga037901d7cb870199ac51d9ad0ef9fd1a}{SSPSR}}
\item 
\+\_\+\+\_\+\+IOM uint32\+\_\+t \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga8826aa84e5806053395a742d38d59d0f}{CSPSR}}
\item 
uint32\+\_\+t {\bfseries RESERVED0} \mbox{[}2U\mbox{]}
\item 
\+\_\+\+\_\+\+IOM uint32\+\_\+t \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga9e5e4421ef9c3d5b7ff8b24abd4e99b3}{ACPR}}
\item 
uint32\+\_\+t {\bfseries RESERVED1} \mbox{[}55U\mbox{]}
\item 
\+\_\+\+\_\+\+IOM uint32\+\_\+t \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga12f79d4e3ddc69893ba8bff890d04cc5}{SPPR}}
\item 
uint32\+\_\+t {\bfseries RESERVED2} \mbox{[}131U\mbox{]}
\item 
\+\_\+\+\_\+\+IM uint32\+\_\+t \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga6c47a0b4c7ffc66093ef993d36bb441c}{FFSR}}
\item 
\+\_\+\+\_\+\+IOM uint32\+\_\+t \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga3f68b6e73561b4849ebf953a894df8d2}{FFCR}}
\item 
\+\_\+\+\_\+\+IM uint32\+\_\+t \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gad6901bfd8a0089ca7e8a20475cf494a8}{FSCR}}
\item 
uint32\+\_\+t {\bfseries RESERVED3} \mbox{[}759U\mbox{]}
\item 
\+\_\+\+\_\+\+IM uint32\+\_\+t \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga4d4cd2357f72333a82a1313228287bbd}{TRIGGER}}
\item 
\+\_\+\+\_\+\+IM uint32\+\_\+t \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gaa4d7b5cf39dff9f53bf7f69bc287a814}{FIFO0}}
\item 
\+\_\+\+\_\+\+IM uint32\+\_\+t \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gab358319b969d3fed0f89bbe33e9f1652}{ITATBCTR2}}
\item 
uint32\+\_\+t {\bfseries RESERVED4} \mbox{[}1U\mbox{]}
\item 
\+\_\+\+\_\+\+IM uint32\+\_\+t \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gaaa573b2e073e76e93c51ecec79c616d0}{ITATBCTR0}}
\item 
\+\_\+\+\_\+\+IM uint32\+\_\+t \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga061372fcd72f1eea871e2d9c1be849bc}{FIFO1}}
\item 
\+\_\+\+\_\+\+IOM uint32\+\_\+t \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gaaa4c823c10f115f7517c82ef86a5a68d}{ITCTRL}}
\item 
uint32\+\_\+t {\bfseries RESERVED5} \mbox{[}39U\mbox{]}
\item 
\+\_\+\+\_\+\+IOM uint32\+\_\+t \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gaf8b7d15fa5252b733dd4b11fa1b5730a}{CLAIMSET}}
\item 
\+\_\+\+\_\+\+IOM uint32\+\_\+t \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga0e10e292cb019a832b03ddd055b2f6ac}{CLAIMCLR}}
\item 
uint32\+\_\+t {\bfseries RESERVED7} \mbox{[}8U\mbox{]}
\item 
\+\_\+\+\_\+\+IM uint32\+\_\+t \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gabc0ecda8a5446bc754080276bad77514}{DEVID}}
\item 
\+\_\+\+\_\+\+IM uint32\+\_\+t \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gad98855854a719bbea33061e71529a472}{DEVTYPE}}
\item 
\+\_\+\+\_\+\+IOM uint32\+\_\+t \mbox{\hyperlink{group___c_m_s_i_s___core___sys_tick_functions_gad092e61fccb6752d3f4adbbd4a7e1567}{PSCR}}
\item 
\+\_\+\+\_\+\+OM uint32\+\_\+t \mbox{\hyperlink{group___c_m_s_i_s___core___sys_tick_functions_gae3a3197c7be6ce07b50fd87cbb02f319}{LAR}}
\item 
\+\_\+\+\_\+\+IM uint32\+\_\+t \mbox{\hyperlink{group___c_m_s_i_s___core___sys_tick_functions_gaf5373794b1c024b28a2a59a9eab6498e}{LSR}}
\item 
\+\_\+\+\_\+\+IM uint32\+\_\+t \mbox{\hyperlink{group___c_m_s_i_s___core___sys_tick_functions_ga01972f64f408cec28320780ca067b142}{TYPE}}
\item 
\+\_\+\+\_\+\+IM uint32\+\_\+t \mbox{\hyperlink{group___c_m_s_i_s___core___sys_tick_functions_ga4c53b48c6bb49037c97742136d14b4f7}{ITFTTD0}}
\item 
\+\_\+\+\_\+\+IOM uint32\+\_\+t \mbox{\hyperlink{group___c_m_s_i_s___core___sys_tick_functions_gafde4a3b09318d1ec4a061d5e479a01bc}{ITATBCTR2}}
\item 
\+\_\+\+\_\+\+IM uint32\+\_\+t \mbox{\hyperlink{group___c_m_s_i_s___core___sys_tick_functions_gaaf0447dd4b2c16dc1db1e2172c9dac8f}{ITFTTD1}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
Structure type to access the Trace Port Interface Register (TPI). 

The documentation for this struct was generated from the following files\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Include/\mbox{\hyperlink{core__armv81mml_8h}{core\+\_\+armv81mml.\+h}}\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Include/\mbox{\hyperlink{core__armv8mbl_8h}{core\+\_\+armv8mbl.\+h}}\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Include/\mbox{\hyperlink{core__armv8mml_8h}{core\+\_\+armv8mml.\+h}}\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Include/\mbox{\hyperlink{core__cm23_8h}{core\+\_\+cm23.\+h}}\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Include/\mbox{\hyperlink{core__cm3_8h}{core\+\_\+cm3.\+h}}\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Include/\mbox{\hyperlink{core__cm33_8h}{core\+\_\+cm33.\+h}}\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Include/\mbox{\hyperlink{core__cm35p_8h}{core\+\_\+cm35p.\+h}}\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Include/\mbox{\hyperlink{core__cm4_8h}{core\+\_\+cm4.\+h}}\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Include/\mbox{\hyperlink{core__cm7_8h}{core\+\_\+cm7.\+h}}\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Include/\mbox{\hyperlink{core__sc300_8h}{core\+\_\+sc300.\+h}}\end{DoxyCompactItemize}
